专利名称：Method and apparatus for performing
multiplication in a processor
发明人：Srikanth Arekapudi,Sudherssen Kalaiselvan申请号：US13309721申请日：20111202公开号：US08868634B2公开日：20141021
专利附图：
摘要：A method and apparatus are described for performing multiplication in aprocessor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bitmultiplicand may be multiplied together over four cycles by merging different partial
product (PP) subsets, generated by a Booth encoder and a PP generator, with feedbacksum and carry results. The logic inputs of a plurality of multiplexers may be selected on acyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum andcarry results. A pair of preliminary sum results stored during one cycle may be outputtedduring a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate afeedback sum result that is merged with a feedback carry result and a PP subset. Finalsum and carry results may be added to generate the product of the multiplier and themultiplicand.
申请人：Srikanth Arekapudi,Sudherssen Kalaiselvan
地址：Sunnyvale CA US,Sunnyvale CA US
国籍：US,US
代理机构：Volpe and Koenig, P.C.
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